In recent years one has seen a proliferation of all-digital phase-locked loops (ADPLL) for RF and high-performance frequency synthesis due to their clear benefits in terms of flexibility, reconfigurability, transfer function precision, settling speed, frequency modulation capability and amenability to integration with digital baseband and application processors. All-digital PLLs have been proposed to achieve savings in both the area cost and the power dissipation. Compared to analog PLLs, all-digital PLLs (ADPLLs) may provide certain aspects in nanoscale CMOS as they dramatically reduce the chip area and further also offer benefits of programmability, capability of extensive self-calibrations and easy portability. In this way power-efficient wireless applications can be envisaged. As the ADPLLs are now employed in high-volume consumer applications, there is a continuous push to provide high performance at low cost and low power consumption.
One substantial problem with conventional ADPLLs is due to the fact that the time-to-digital-converter (TDC) of an ADPLL is traditionally power hungry. In the time domain, the time-to-digital converter acts as phase detector to compare the phase leading/lagging of the input reference clock signal and the output high frequency clock signal.
In low power all-digital phased locked loops (AD-PLL) the clock edges of the digitally controlled oscillator (DCO) are retimed via a delay-to-time converter (DTC), such that that power hungry time-to-digital-converter (TDC) can be reduced in size. However, the actual delay of the elements of a DTC is a function of the process power supply voltage and temperature (PVT). These variations are in the order of ±20% of the designed delay. Therefore the delay elements need to be calibrated, as a misaligned DTC causes degradation of the performance and in some cases renders the AD-PLL inoperable. Conventional calibration algorithms require long settling times and do not converge for small fractional settings.
An example of the traditional approach centered around a time-to-digital-converter is found in the paper “A low-power all-digital PLL architecture based on phase prediction” (J.Zhuang et al., IEEE Int'l Conf. on Electronics, Circuits and Systems, pp. 797-800, December 2012). It presents a phase-prediction ADPLL architecture, which exploits an implicit prediction of the next-edge timing relationship between the variable clock (CKV) and reference clock (FREF) based on current state variables to reduce complexity and power consumption. FIG. 1A shows a simplified diagram of this architecture. The reference phase (PHR) generator 10 accumulates the frequency control word (FCW) at each FREF cycle to provide a digital representation of the desired DCO clock (i.e., CKV) phase. The reference phase generator 10 splits the reference phase PHR into an integer (PHR_I) and a fractional (PHR_F) part for a separate detection of the integer phase error (PHE_I) and fractional phase error (PHE_F). The detection of PHE_I, which may be disabled in the phase-locked condition, can be done by computing the difference between PHR_I and DCO variable phase (PHV) that is the output of a counter (for simplicity, not shown in the figure) triggered by CKV edges and sampled at every reference edge. In the fractional phase detection path the reference clock (FREF) is delayed using a digital-to-time converter (DTC) 30. The DTC overall delay is controlled by the output signal of the estimator block 20, i.e. DTC_ctrl, based on the PHR_F and the sign value of the PHE_F. The relation between the intended delay in a fractional PHR_F of the FREF and the actual physical delay set by the DTC is given by the gain K_dtc of the DTC line. This gain K_dtc is estimated in estimator block 20, where also the phase is predicted. In the phase-locked condition, as shown in FIG. 1B, the delayed reference clock FREF_dly is dynamically phase aligned with CKV, thus a narrow-range TDC 40 can be employed to quantize the time difference between FREF_dly and CKV edges to generate the fractional part of the digital phase error, PHE_F. In some examples, techniques described herein may reduce the timing range and thus the complexity of the fractional part of the phase detection. An error in the estimation of K_dtc (which, as already mentioned, provides the link between the intended delay and the actual physically set delay) causes phase errors and can cause the ADPLL to unlock.
A simplified block diagram of the applied gain estimation algorithm is shown in FIG. 2. In the phase prediction block a zero mean fractional part (PHR_F) of the reference phase received at its input is scaled with a factor a and multiplied by the scaled sign of PHE_F to generate the estimation error (see section 210). This error is filtered by an IIR filter 220 and the IIR filter output is multiplied in section 230 by the step size d of the iterative adaptation algorithm. After integration in section 240 a gain estimation K_dtc is obtained. The K_dtc estimation block is triggered by the reference clock running at the reference rate and may be disabled once the K_dtc estimation is done, or kept running in order to track the K_dtc variation due to temperature and voltage changes.
Some conventional techniques making use of the algorithm shown in FIG. 2, however, suffer from long convergence times (200 μs and more). Such a calibration time makes it unsuitable for fast frequency switching in, for example, an architecture as used in a Bluetooth low Energy radio where transmit and receive switching requires the PLL to jump 500 MHz between transmitter and receiver. Moreover, this technique often is very unstable at small fractional settings where it may not converge at all. An illustration of the stability problem at small fractional parts is provided in FIG. 3. As can be seen in the figure, the estimated K_dtc 310 clearly cannot converge to the correct value 320.
Hence, there is a need for an approach wherein this drawback is avoided or overcome.